Last Updated on Sunday, 14 May 2017 07:40

Overview

The Common I/O Bus (or CIO) is the internal peripheral bus defined in the AT&T 3B2 architecture.  It exists to connect primarily I/O devices to the system planar and not to provide memory or multiprocessor expansion.  External card interfaces for those two extended  functions were established with the 500 series.   The CIO bus was established with the very first 3B2 machine (300 series) and persisted across all models in the line.  However some cards developed later in version 3 architecture were not compatible with earlier systems.  For example, 300/400 series machines cannot use a CIO SCSI card as a boot device as the 300/400 system ROMs did not have specific protocol knowledge of the SCSI card.

CIO is a bus interface standard that involves a hardware level transport and a basic command set to a higher level application stack on both sides.  The cards themselves are intelligent with most running an Intel 80186 embedded processor on each card.  In many ways, CIO was ahead of it’s time in that it allowed each card to independently bus-master, via the on-board 80186, to the 3B2 system board main memory.  A PIO access scheme was defined, however it was mainly used to wake-up either the host or peripheral 80186 to service CIO request queues in main memory – with each side having direct access.  Most of the CIO cards were heavily derived from a common reference design by AT&T’s core architecture group and were nearly identical in their functional layout – including identical 80186, 16KB ROM, 128KB RAM, most of the glue logic and buffering, and a significant portion of the card ROM firmware.  They mostly differed in application specific supporting devices such as a UART, network MAC, SCSI interface chip-set, etc.

Signal overview

The CIO bus itself contains a 24-bit address bus and a 16-bit data bus shared by all cards in the stack.  Each card slot has an independent chip-select (CS) decoded by different regions of the host CPU’s (WE32K) 32-bit physical view.  Arbitration for bus mastering and interrupt request handling was done in a cascade fashion with a request-out and grant-in signal chained from one card slot to the next.  Slot position defined the priority order for both arbitration and interrupt priority within each tier with three tiers of interrupt signals.

CIO Pin-Out

Electrical Overview

Pinouts

PIO map

Conceivably, additional hardware (cost and space) could be used to detect such a
situation and in turn temporarily back off the peripheral’s microprocessor (or